 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Ordering number : EN5877 CMOS IC LC72720N, 72720NM Single-Chip RDS Signal-Processing System LSI Overview The LC72720N and LC72720NM are single-chip system ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision error correction technique. Package Dimensions unit: mm 3067-DIP24S [LC72720N] Functions * Band-pass filter: Switched capacitor filter (SCF) * Demodulator: RDS data clock regeneration and demodulated data reliability information * Synchronization: Block synchronization detection (with variable backward and forward protection conditions) * Error correction: Soft-decision/hard-decision error correction * Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory * Data I/O: CCB interface (power on reset) SANYO: DIP24S unit: mm 3045B-MFP24 [LC72720NM] Features * Error correction capability improved by soft-decision error correction * The load on the microcontroller can be reduced by storing decoded data in the on-chip data buffer RAM. * Two synchronization detection circuits provide continuous and stable detection of the synchronization timing. * Data can be read out starting with the backwardprotection block data after a synchronization reset. * Fully adjustment free * Operating power-supply voltage: 4.5 to 5.5 V * Operating temperature: -40 to +85C * Packages: DIP24S, MFP24 * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. SANYO: MFP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 51398RM (OT) No. 5877-1/14 LC72720N, 72720NM Pin Assignment Block Diagram T3 to T7 No. 5877-2/14 LC72720N, 72720NM Pin Descriptions Pin No. Pin name Function I/O Equivalent circuit 1 VREF Reference voltage output (Vdda/2) Output 2 MPXIN Baseband (multiplexed) signal input Input 5 FLOUT Subcarrier output (filter output) Output 6 CIN Subcarrier input (comparator input) Input 3 4 12 Vdda Vssa XOUT Analog system power supply (+5 V) Analog system ground Crystal oscillator output (4.332/8.664 MHz) -- -- Output -- -- 13 XIN Crystal oscillator input (external reference signal input) 7 T1 Test input (This pin must always be connected to ground.) Test input (standby control) 0: Normal operation, 1: Standby state (crystal oscillator stopped) Test I/O (RDS clock output) Test I/O (RDS data output) Test I/O (soft-decision control data output) Test I/O (error status output, regenerated carrier output, error block count output) Test I/O (Error correction status output, SK detection output, error block count output) Block synchronization detection output RDS detection output Data output Clock input Data input Chip enable Synchronization and RAM address reset (active high) Digital system power supply (+5 V) Digital system ground Serial data interface (CCB) Input 8 9 10 11 16 T2 T3 (RDCL) T4 (RDDA) T5 (RSFT) T6 (ERROR/57K/BE1) I/O* 17 18 19 20 21 22 23 24 14 15 T7 (CORREC/ARI-ID/BE0) SYNC RDS-ID DO CL DI CE SYR Vddd Vssd Output Input -- -- -- -- Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications. No. 5877-3/14 LC72720N, 72720NM Specifications Absolute Maximum Ratings at Ta = 25C, Vssd = Vssa = 0 V Parameter Maximum supply voltage Symbol VDD max VIN1 max Maximum input voltage VIN2 max VIN3 max VO1 max Maximum output voltage VO2 max VO3 max IO1 max Maximum output current IO2 max IO3 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Conditions Vddd, Vdda (Vdda Vddd + 0.3 V) CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC XIN MPXIN, CIN DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 XOUT FLOUT DO, T3, T4, T5, T6, T7 XOUT, FLOUT SYNC, RDS-ID Ta 85C DIP24S: MFP24: Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to Vddd +0.3 -0.3 to Vdda +0.3 -0.3 to +7.0 -0.3 to Vddd +0.3 -0.3 to Vdda +0.3 6.0 3.0 20.0 350 300 -40 to +85 -55 to +125 Unit V V V V V V V mA mA mA mW mW C C Note: A capacitor of at least 1000 pF must be inserted between the power supply pins Vdd and Vss. Allowable Operating Ranges at Ta = -40 to +85C, Vssd = Vssa = 0 V Parameter Symbol VDD1 VDD2 VIH VIL VO VIN1 Input amplitude VIN2 VXIN Guaranteed crystal oscillator frequencies Crystal oscillator frequency deviation Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time CE high-level time Data latch change time Xtal TXtal tSU tHD tCL tCH tEL tES tEH tCE tLC tDC Data output time tDH DO, CL: Differs depending on the value of the pull-up resistor used. DO, CE: Differs depending on the value of the pull-up resistor used. Conditions Vddd, Vdda (Vddd = Vdda) Vddd: Serial data hold voltage CL, DI, CE, SYR, T1, T2 CL, DI, CE, SYR, T1, T2 DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 MPXIN : f = 57 2 kHz MPXIN : 100% modulation composite XIN XIN, XOUT : CI 120 (XS = 0) XIN, XOUT : CI 70 (XS = 1) XIN, XOUT : fO = 4.322 MHz, 8.664 MHz DI, CL DI, CL CL CL CE, CL CE, CL CE, CL CE 0.75 0.75 0.75 0.75 0.75 0.75 0.75 20 1.15 0.46 0.46 100 400 4.332 8.664 100 1500 Ratings min 4.5 2.0 0.7 Vddd 0 6.5 0.3 Vddd 6.5 50 typ 5.0 max 5.5 Unit V V V V V mVrms mVrms mVrms MHz MHz ppm s s s s s s s ms s s s Supply voltage Input high-level voltage Input low-level voltage Output voltage Electrical Characteristics in the allowable operating ranges Parameter Symbol Rmpxin Rcin Rf fc Conditions MPXIN-Vssa : f = 57 kHz CIN-Vssa : f = 57 kHz XIN FLOUT 56.5 2.5 28 30 40 50 2.5 Ratings min typ 23 100 1.0 57.0 3.0 31 57.5 3.5 34 max Unit k k M kHz kHz dB dB dB dB V Input resistance Internal feedback resistance Center frequency -3 dB bandwidth Gain BW - 3 dB FLOUT Gain Att1 MPXIN-FLOOUT : f = 57 kHz FLOUT : f = 7 kHz FLOUT : f < 45 kHz, f > 70 kHz FLOUT : f < 20 kHz VREF : Vdda = 5 V Stop band attenuation Att2 Att3 Reference voltage output Vref Continued on next page. No. 5877-4/14 LC72720N, 72720NM Continued from preceding page. Parameter Hysteresis Output low-level voltage Symbol VHIS VOL1 VOL2 IIH1 IIH2 IIL1 IIL2 IOFF Idd Conditions CL, DI, CE, SYR, T1, T2 DO, T3, T4, T5, T6, T7 : I = 2 mA SYNC, RDS-ID : I = 8 mA CL, DI, CE, SYR, T1, T2 : VI = 6.5 V XIN : VI = Vddd CL, DI, CE, SYR, T1, T2 : VI = 0 V XIN : VI = 0 V DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 : VO = 6.5 V Vddd + Vdda 12 2.0 2.0 Ratings min typ 0.1 Vddd 0.4 0.4 5.0 11 5.0 11 5.0 max Unit V V V A A A A A mA Input high-level current Input low-level current Output off leakage current Current drain CCB Output Data Format * Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data. * Any number of 32-bit output data blocks can be output consecutively. * When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data consecutively. * If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted. However, if only the last bit remains to be read, it will not be possible to reread that whole block. * The check bits (10 bits) are not output. * To judge whether or not the data is valid, refer to the error information flags E0 to E2, but the offset word detection flags (OWD) should never be reffered to. * If the first four-bits are not "1010", since the readout data is invalid, readout operation must be halted. CCB address 6C Output data/first bit Last bit (8) RDS data (7) Error information flags (6) Synchronization established flag (5) ARI (SK) detection flag (4) RAM data remaining flag (3) Consecutive RAM read out possible flag (2) Offset word information flag (1) Offset word detection flag Fixed pattern (1010) 1. Offset word detection flag (1 bit): OWD OWD 1 0 Offset word detection Detected Not detected (protection function operating) 2. Offset word information flag (3 bits): B0 to B2 BBB 210 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Offset word A B C C' D E Unused Unused No. 5877-5/14 LC72720N, 72720NM 3. Consecutive RAM readout possible flag (1 bit): RE RE 1 0 RAM data information The next data to be read out is in RAM. This data item is the last item in RAM, and the next data is not present. 4. RAM data remaining flag (2 bits): RF0, RF1 RF1 0 0 1 1 RF0 0 1 0 1 Remaining data in RAM (number of blocks) 1 to 7 8 to 15 16 to 23 24 Note: This value is meaningful only when RE is 1. When RE is 0, there is no data in RAM, even if RF is 00. If a synchronization reset was applied using SYR, then the backward protection block data that was written to memory is also counted in this value. 5. ARI (SK) detection flag (1 bit): ARI ARI 1 0 SK signal Detected Not detected 6. Synchronization established flag (1 bit): SYC SYC 1 0 Synchronization detection Synchronized Not synchronized Note: This flag indicates the synchronization state of the circuit at the point where the data block being output was received. On the other hand, the SYNC pin (pin 18) output indicates the current synchronization state of the circuit. 7. Error information flags (3 bits): E0 to E2 EEE 210 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 Number of bits corrected 0 (no errors) 1 2 3 4 5 0 Correction not possible 1 Unused Note: If the number of errors exceeds the value of the EC0 to EC2 setting (see the section on the CCB input format), the error information flags will be set to the "Correction not possible" value. Take the data as invalid when EC0 - EC2 = 011 (correction not possible). 8. RDS data (16 bits): D0 to D15 This data is output with the MSB first and the LSB last. Caution: When error correction was not possible, the input data is output without change. No. 5877-6/14 LC72720N, 72720NM CCB Input Data Format [1] CCB address 6A IN1 data, first bit (11) Circuit control (5) Error correction method setting (4) RAM write control (3) Synchronization and RAM address reset (2) Synchronization detection method setting (1) Synchronization protection method setting [2] CCB address 6B IN2 data, first bit (10) Test mode settings (9) Output pin settings (8) RDS/RBDS selection (7) Demodulation circuit phase control (6) Crystal oscillator frequency selection (11) Circuit control Note: The bits labeled with an asterisk must be set to 0. 1. Synchronization protection (forward protection) method setting (4 bits): FS0 to FS3 FS3 = 0: If offset words in the correct order could not be detected continuously during the number of blocks specified by FS0 to FS2, take that to be a lost synchronization state. FS3 = 1: If blocks with uncorrectable errors were received consecutively during the number of blocks specified by FS0 to FS2, take that to be a lost synchronization state. FFF SSS 012 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 Condition for detecting lost synchronization 0 If 3 consecutive blocks matching the FS3 condition are received. 0 If 4 consecutive blocks matching the FS3 condition are received. 0 If 5 consecutive blocks matching the FS3 condition are received. 0 If 6 consecutive blocks matching the FS3 condition are received. 1 If 8 consecutive blocks matching the FS3 condition are received. 1 If 10 consecutive blocks matching the FS3 condition are received. 1 If 12 consecutive blocks matching the FS3 condition are received. 1 If 16 consecutive blocks matching the FS3 condition are received. Initial value: FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0 2. Synchronization detection method setting (1 bit): BS BS 0 1 Synchronization detection conditions If, during 3 blocks, 2 blocks of offset words were detected in the correct order. If the offset words were detected in the correct order in 2 consecutive blocks. Initial value: BS = 0 No. 5877-7/14 LC72720N, 72720NM 3. Synchronization and RAM address reset (1 bit): SYR SYR 0 1 Synchronization detection circuit Normal operation (reset cleared) Forced to the unsynchronized state (synchronization reset) RAM Normal write (See the description of the OWE bit.) After the reset is cleared, start writing from the data prior to the establishment of synchronization, i.e. the data in backward protection. Initial value: SYR =0 Note: 1. To apply a synchronization reset, set SYR to 1 temporarily using the CCB, and then set it back to 0 again using the CCB. The circuit will start synchronization capture operation at the point SYR is set to 0. 2. The SYR pin (pin 24) also provides an identical reset control operation. Applications can use either method. However, the control method that is not used must be set to 0 at all times. Any pulse with a width of over 250 ns will suffice. 3. A reset must be applied immediately after the reception channel is changed. If a reset is not applied, reception data from the previous channel may remain in memory. 4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding the establishment of synchronization. 4. RAM write control (1 bit): OWE OWE 0 1 RAM write conditions Only data for which synchronization had been established is written. Data for which synchronization has not been established (unsynchronized data) is also written. (However, this applies when SYR = 0.) Initial value: OWE = 0 5. Error correction method setting (5 bits): EC0 to EC4 EEE CCC 012 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 Number of bits corrected EE CC 34 0 1 0 1 0 0 1 1 Soft-decision setting Mode 0: Hard decision Mode 1: Soft decision A Mode 2: Soft decision B Illegal value 0 0 (error detection only) 0 0 0 1 1 1 1 1 or fewer bits 2 or fewer bits 3 or fewer bits 4 or fewer bits 5 or fewer bits Illegal value Illegal value Initial values: EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1 Note: 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors. 2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction. 6. Crystal oscillator frequency selection (1 bit): XS XS = 0: 4.332 MHz XS = 1: 8.664 MHz Initial value: XS = 0 7. Demodulation circuit phase control (2 bits): PL0, PL1 PL0 0 1 PL1 0/1 0 1 Demodulation circuit phase control Initial values: PL0 = 0, PL1 = 1 Note: 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier. However, the initial phase following a synchronization reset is set by PL1. 2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90 (PL1 = 0) or 0 (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the RDS data is reproduced by detecting at a phase of 90 with respect to the reproduced carrier. When ARI is present, PL1 should be set to 1, since detection is at 0. In cases where the ARI presence is known in advance, more stable reproduction can be achieved by fixing the demodulation phase in this manner. No. 5877-8/14 LC72720N, 72720NM 8. RDS/RBDS (MMBS) selection (1 bit): RM RM 0 1 RBDS support None Provided Decoding method Only RDS data is decoded correctly (Offset word E is not detected.) RDS and MMBS data is decoded correctly (Offset word E is also detected.) Initial value: RM = 0 9. Output pin settings (3 bits): PT0 to PT2 These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins. PPP Mode T 0 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 T 1 0 0 1 1 0 0 1 1 T 2 0 0 0 0 1 1 1 1 T3 RDCL -- q q q -- q q q T4 RDDA -- q q q -- q q q T5 RSFT -- q q q -- q q q ERROR -- -- -- q -- -- -- q T6 57K -- -- q -- -- -- q -- BE1 -- -- -- -- q -- -- -- CORREC -- -- -- q -- -- -- q T7 ARI-ID -- -- q -- -- -- q -- BE0 -- -- -- -- q -- -- -- --: Open, q , q: Output enabled (q = reverse polarity) Initial values: PT0 = 1, PT1 = 1, PT2 = 0 (mode 3) Note: 1. When PT2 is set to 1, the polarity of the T3 (RDCL), T6 (ERROR/57K), T7 (CORREC/ARI-ID) SYNC, and RDS-ID pins changes to active high. 2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors to output data. Pin T3 (RDCL) PT2 = 0 PT2 = 1 Data (RDDA and RSFT) changes on this pin's rising edge. Data (RDDA and RSFT) changes on this pin's falling edge. Mode 2 (PT2 = 0) No SK SK present Pin T7 (ARI-ID) High (1) Low (0) Mode 3 (PT2 = 0) Correction not possible Errors corrected No errors Pin T6 (ERROR) Low (0) High (1) High (1) Pin T7 (CORREC) Low (0) Low (0) High (1) Mode 4 Number of error blocks (B) B=0 1 B 20 20 < B 40 40 < B 48 Pin T6 (BE1) Low (0) Low (0) High (1) High (1) Pin T7 (BE0) Low (0) High (1) Low (0) High (1) These pins indicate the number of blocks in a set of 48 blocks that had errors before correction. The output polarity of these pins is fixed at the values listed in the table. No. 5877-9/14 LC72720N, 72720NM Mode (PT2 = 0) 0 to 2 3 The SYNC pin When synchronized: Low (0). When unsynchronized: High (1) When synchronized: Goes high for a fixed period (421 s) at the start of a block and then goes low. When unsynchronized: High (1) Note: The output indicates the synchronization state for the previous block. When PT2 = 0 No RDS RDS present The RDS-ID pin High (1) Low (0) 10. Test mode settings (4 bits): TS0 to TS3 Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0 (Applications must set these bits to the above values.) Note: T1 and T2 pins (pins 7 and 8) are related to test mode as follows: Pin T1 0 0 1 Pin T2 0 1 0/1 IC operation Normal operating mode Standby mode (crystal oscillator stopped) IC test mode These states are user settable Users cannot use this state Notes T1 pin must be tied to VSS (0 V). 11. Circuit control (2 bits): CT0 and CT1 Item CT0 CT1 RSFT control RDS-ID detection condition Control When set to 1, soft-decision control data (RSFT) is easier to generate. When set to 1, the RDS-ID detection conditions are made more restrictive. Initial values: CT0 = 0, CT1 = 0 RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing Timing 1 (modes 1 to 3, PT2 = 0) RDCL output RDDA output Note: When PT2 = 0, RDDA and RSFT must be aquired on the falling edge of RDCL. RSFT output Timing 2 (mode 3, PT2 = 0) Input data Sync NG Sync OK Sync OK Sync OK Sync OK Sync OK Uncorrectable Sync NG Uncorrectable Sync NG Error crrection Data corrected No errors No errors Data corrected SYNC output ERROR output CORREC output No. 5877-10/14 LC72720N, 72720NM Serial Data Input and Output Methods Data is input and output using the CCB (computer control bus), which is the Sanyo audio IC serial bus format. This IC adopts an 8-bit address CCB format. (LSB) I/O mode 1 2 3 IN1 (6A) IN2 (6B) OUT (6C) B0 0 1 0 B1 1 1 0 B2 0 0 1 Address B3 1 1 1 A0 0 0 0 A1 1 1 1 (MSB) A2 1 1 1 A3 0 0 0 Comment * Control data input mode, also referred to as "serial data input" mode. * This is a 16-bit data input mode. * Control data input mode, also referred to as "serial data input" mode. * This is a 16-bit data input mode. * Data output mode, also referred to as "serial data output" mode. * Data output during clock input. I/O mode determined For the CL normal high state For the CL normal low state Serial data input (IN1, IN2) tSU, tHD, tEL, tES, tEH 0.75 s tLC < 1.15s tCE < 20 ms CL: Normal high Internal data CL: Normal low Internal data No. 5877-11/14 LC72720N, 72720NM Serial data output (OUT) tSU, tHD, tEL, tES, tEH 0.75 s tDC, tDH < 0.46 s tCE < 20 ms CL: Normal high CL: Normal low DO Notes:1. Since the DO pin is an n-channel open-drain output, the transition times (tDC, tDH) will differ with the value of the pull-up resistor used. 2. The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface. (However, we recommend connecting the DO and CE pins separately if the number of available microcontroller ports allows it.) Serial data timing CL: Normal high Intenal data latch Old New CL: Normal low Intenal data latch Old New No. 5877-12/14 LC72720N, 72720NM Ratings min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 20 1.15 DO, CL DO, CE Differs with the value of the pull-up resistor used. 0.46 0.46 typ max Parameter Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time CE high-level time Data latch transition time Data output time Symbol tSU tHD tCL tCH tEL tES tEH tCE tLC tDC tDH DI, CL DI, CL CL CL CE, CL CE, CL CE, CL CE Conditions Unit s s s s s s s ms s s s DO pin operation This IC incorporates a RAM data buffer that can hold up to 24 blocks of data. At the point where one block of data is written to this RAM, the IC issues a read request by switching the DO pin from high to low. The DO pin always goes high for a fixed period (Tdo = 265 s) after a readout and CE goes low. When all the data in the data buffer has been read out, the DO pin is held in the high state until a new block of data has been written to the RAM. If there is data that has not yet been read remaining in the data buffer, the DO pin goes low after the Tdo time has elapsed. After a synchronization reset, the DO pin is held high until synchronization is established. It goes low at the point where the IC synchronizes. 1. When the DO pin is high following the 265 s period (Tdo) after data is read out Here, the buffer is in the empty state, i.e. the state where new data has not been written. After this, when the DO pin goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 480 ms of DO going low. CE pin DO pin (Last data) - 1 Last data New data DO check (Tdo < T) 2. When the DO pin is low following the 265 s period (Tdo) after data is read out Here, there is data that has not been read out remaining in the data buffer. In this case, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms of DO going low. (Note that this is the worst case condition.) CE pin DO pin (Last data) - 2 (Last data) - 1 Last data DO check (Tdo < T) Notes: 1. Although an application can determine whether or not there is data remaining in the buffer by checking the DO level with the above timing, checking the RE and RF flags in the serial data is a preferable method. 2. Applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data continuously as described above. When using this method, if an application references the RE and RF flags in the data while reading out data, it can determine the amount of data remaining. However, the length of the period for data readout (the period the CE pin remains high) must be kept under 20 ms. 3. If the DO pin is shared with other ICs that use the CCB interface, the application must identify which IC issued the readout request. One method is to read out data from the LC72720 and either check whether meaningful data has been read (if the LC72720 is not requesting a read, data consisting of all zeros will be read out) or check whether the DO level goes low within the 256 s following the completion of the read (if the DO pin goes low, then the request was from another IC). No. 5877-13/14 LC72720N, 72720NM Sample Application Circuit Notes: 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed. 2. If the SYR pin is unused, it must be connected to ground. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5877-14/14 |
Price & Availability of LC72720NM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |